000184936 001__ 184936
000184936 005__ 20230219174620.0
000184936 0247_ $$2CORDIS$$aG:(EU-Grant)687220$$d687220
000184936 0247_ $$2CORDIS$$aG:(EU-Call)H2020-COMPET-2015$$dH2020-COMPET-2015
000184936 0247_ $$2originalID$$acorda__h2020::687220
000184936 035__ $$aG:(EU-Grant)687220
000184936 150__ $$aValidation of European high capacity rad-hard FPGA and software tools$$y2016-01-01 - 2020-08-31
000184936 371__ $$aCOMPUTADORAS  REDES E INGENIERIA SA$$bCRISA$$dSpain$$ehttp://www.crisa.es$$vCORDIS
000184936 371__ $$aSTMicroelectronics (Switzerland) - STMicroelectronics (France)$$bST$$dFrance$$ehttp://www.st.com/content/st_com/en.html$$vCORDIS
000184936 371__ $$aAIRBUS DEFENCE AND SPACE GMBH$$dGermany$$ehttp://www.airbus-group.com$$vCORDIS
000184936 371__ $$aAIRBUS DS GMBH$$dGermany$$ehttp://www.airbusdefenceandspace.com$$vCORDIS
000184936 371__ $$aAIRBUS DEFENCE AND SPACE SAS$$dFrance$$ehttp://www.airbusdefenceandspace.com$$vCORDIS
000184936 371__ $$aNANOXPLORE$$dFrance$$ehttp://www.nanoxplore.com$$vCORDIS
000184936 371__ $$aSTMICROELECTRONICS GRENOBLE 2 SAS$$bSTGNB 2 SAS$$dFrance$$ehttp://www.st.com$$vCORDIS
000184936 371__ $$aUniversity of Seville$$bUniversity of Seville$$dSpain$$ehttp://www.us.es/eng$$vCORDIS
000184936 371__ $$aPolytechnic University of Turin$$bPolytechnic University of Turin$$dItaly$$ehttp://www.polito.it/$$vCORDIS
000184936 371__ $$aTHALES ALENIA SPACE ESPANA, SA$$bTAS-E$$dSpain$$vCORDIS
000184936 371__ $$aTHALES ALENIA SPACE FRANCE SAS$$bTHALES ALENIA SPACE FRANCE$$dFrance$$ehttp://www.thalesaleniaspace.com$$vCORDIS
000184936 372__ $$aH2020-COMPET-2015$$s2016-01-01$$t2020-08-31
000184936 450__ $$aVEGAS$$wd$$y2016-01-01 - 2020-08-31
000184936 5101_ $$0I:(DE-588b)5098525-5$$2CORDIS$$aEuropean Union
000184936 680__ $$aVEGAS proposes to address the key challenge of European non-dependence and competitivness regarding rad-hard FPGA for space applications. VEGAS will evaluate (following ESCC rules) and validate the first rad-hard FPGA in 65nm to directly compete with the US offering and reach TRL 7. 
The VEGAS project sets clear and measurable main objectives to reach a TRL 7 from TRL 5 (end of BRAVE project) as follows:
1. Validation by end users of rad-hard FPGA developped under the BRAVE project – TRL 6 achieved
2. Space evaluation of the first rad-hard FPGA developped under the BRAVE project – TRL 7 achieved
3. Software CAD tools improvement by including timing and SEE mitigation tools

VEGAS will complement the ongoing ESA funded BRAVE project. BRAVE covers all hardware and software development to reach a first prototype of NG-FPGA-MEDIUM (30k LUTs) and NG-FPGA-LARGE (130k LUTs) . VEGAS will cover all required steps to ESCC evaluate / validate the BRAVE NG-FPGA-MEDIUM and NG-FPGA-LARGE prototype and add additional software tools to reach a competitive software offering.
000184936 909CO $$ooai:juser.fz-juelich.de:282201$$pauthority$$pauthority:GRANT
000184936 909CO $$ooai:juser.fz-juelich.de:282201
000184936 970__ $$aoai:dnet:corda__h2020::4c3f1b1d0d7efebe6f6eb1e708030df8
000184936 980__ $$aG
000184936 980__ $$aCORDIS
000184936 980__ $$aAUTHORITY