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| 001 | 184936 | ||
| 005 | 20230219174620.0 | ||
| 024 | 7 | _ | |a G:(EU-Grant)687220 |d 687220 |2 CORDIS |
| 024 | 7 | _ | |a G:(EU-Call)H2020-COMPET-2015 |d H2020-COMPET-2015 |2 CORDIS |
| 024 | 7 | _ | |a corda__h2020::687220 |2 originalID |
| 035 | _ | _ | |a G:(EU-Grant)687220 |
| 150 | _ | _ | |a Validation of European high capacity rad-hard FPGA and software tools |y 2016-01-01 - 2020-08-31 |
| 371 | _ | _ | |a COMPUTADORAS REDES E INGENIERIA SA |b CRISA |d Spain |e http://www.crisa.es |v CORDIS |
| 371 | _ | _ | |a STMicroelectronics (Switzerland) - STMicroelectronics (France) |b ST |d France |e http://www.st.com/content/st_com/en.html |v CORDIS |
| 371 | _ | _ | |a AIRBUS DEFENCE AND SPACE GMBH |d Germany |e http://www.airbus-group.com |v CORDIS |
| 371 | _ | _ | |a AIRBUS DS GMBH |d Germany |e http://www.airbusdefenceandspace.com |v CORDIS |
| 371 | _ | _ | |a AIRBUS DEFENCE AND SPACE SAS |d France |e http://www.airbusdefenceandspace.com |v CORDIS |
| 371 | _ | _ | |a NANOXPLORE |d France |e http://www.nanoxplore.com |v CORDIS |
| 371 | _ | _ | |a STMICROELECTRONICS GRENOBLE 2 SAS |b STGNB 2 SAS |d France |e http://www.st.com |v CORDIS |
| 371 | _ | _ | |a University of Seville |b University of Seville |d Spain |e http://www.us.es/eng |v CORDIS |
| 371 | _ | _ | |a Polytechnic University of Turin |b Polytechnic University of Turin |d Italy |e http://www.polito.it/ |v CORDIS |
| 371 | _ | _ | |a THALES ALENIA SPACE ESPANA, SA |b TAS-E |d Spain |v CORDIS |
| 371 | _ | _ | |a THALES ALENIA SPACE FRANCE SAS |b THALES ALENIA SPACE FRANCE |d France |e http://www.thalesaleniaspace.com |v CORDIS |
| 372 | _ | _ | |a H2020-COMPET-2015 |s 2016-01-01 |t 2020-08-31 |
| 450 | _ | _ | |a VEGAS |w d |y 2016-01-01 - 2020-08-31 |
| 510 | 1 | _ | |0 I:(DE-588b)5098525-5 |a European Union |2 CORDIS |
| 680 | _ | _ | |a VEGAS proposes to address the key challenge of European non-dependence and competitivness regarding rad-hard FPGA for space applications. VEGAS will evaluate (following ESCC rules) and validate the first rad-hard FPGA in 65nm to directly compete with the US offering and reach TRL 7.
The VEGAS project sets clear and measurable main objectives to reach a TRL 7 from TRL 5 (end of BRAVE project) as follows:
1. Validation by end users of rad-hard FPGA developped under the BRAVE project – TRL 6 achieved
2. Space evaluation of the first rad-hard FPGA developped under the BRAVE project – TRL 7 achieved
3. Software CAD tools improvement by including timing and SEE mitigation tools
VEGAS will complement the ongoing ESA funded BRAVE project. BRAVE covers all hardware and software development to reach a first prototype of NG-FPGA-MEDIUM (30k LUTs) and NG-FPGA-LARGE (130k LUTs) . VEGAS will cover all required steps to ESCC evaluate / validate the BRAVE NG-FPGA-MEDIUM and NG-FPGA-LARGE prototype and add additional software tools to reach a competitive software offering. |
| 909 | C | O | |o oai:juser.fz-juelich.de:282201 |p authority:GRANT |p authority |
| 909 | C | O | |o oai:juser.fz-juelich.de:282201 |
| 970 | _ | _ | |a oai:dnet:corda__h2020::4c3f1b1d0d7efebe6f6eb1e708030df8 |
| 980 | _ | _ | |a G |
| 980 | _ | _ | |a CORDIS |
| 980 | _ | _ | |a AUTHORITY |
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